Bandwidth and capacity of memory systems based on commodity dual-inline memory modules (DIMM) are severely limited by the parallel stub bus between the modules and the memory controller. In order to maintain signal integrity, the maximum number of DIMMs per channel had to be reduced with the market entrance of every new dynamic random access memory (DRAM) generation. Fully buffered DIMMs (FBDIMM) eliminate this limitation by replacing the parallel stub bus by a serial, point-to-point link with a repeater device (advanced memory buffer AMB) residing on every FBDIMM, see e.g., “FB-DIMM High Speed Differential PTP Link at 1.5V—Specification”, JEDEC, December 2005. While solving the bandwidth-capacity problem, FBDIMM systems potentially increase the memory latency. Keeping the pass-through latency below 3 ns, combined with careful command sequencing alleviates only the latency problem as described in paper to B. Ganesh et al., “Fully-Buffered DIMM Memory Architectures: Understanding, Mechanisms, Overhead and Scalings”, IEEE Int. Symp. On High Performance Computer Architecture, pp. 109-120, February 2007. The main barrier for the wide acceptance of FBDIMM, however, remains the high power consumption of the AMB. Current AMBs tend to consume more than 8 W, as shown in the document of Intel Corporation, “Intel 6400/6402 Advanced Memory Buffer Datasheet”, pp. 38-42, October 2006, with the high speed serial link alone dissipating 4 W, as described in paper to H. Partovi et. al, “Data Recovery and Retiming for the Fully Buffered DIMM 4.8 Gb/s Serial Links”, ISSCC Dig. Tech. Papers, pp. 336-337, February 2006. A significant reduction of AMB power consumption, and most importantly its high speed serial link delivering up to 115 Gb/s, remains a critical undertaking in the design of high bandwidth and high capacity memory systems.
The basic functionality of the AMB is described in more detail in the background section of the patent application Ser. No. 11/790,707 “PROGRAMMABLE ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) STRUCTURE WITH MERGING CAPABILITY” to Reitlingshoefer et al. filed Apr. 27, 2007, which is incorporated herein by reference. As described in this application, the AMB requires numerous timing alignment circuits, both for the serial data channels and for the common reference clock. The timing alignment circuits may each include a phase lock loop (PLL) which in turn may include a voltage controlled oscillator (VCO).
FIG. 1 is a block diagram of a conventional PLL 100 of the prior art, for generating a multiphase clock output 102 that is aligned in phase and frequency with a reference clock input 104. The PLL 100 comprises a phase/frequency detector (PFD) 106, a loop filter 108, a divide-by-Z circuit 110, and a VCO 112. The multiphase clock output 102 may be generated by decoding the states of the divide-by-Z circuit 110. An alternative multiphase clock output 102′ may be obtained by decoding the states of the VCO 112, assuming the VCO 112 is constructed in a suitable configuration, for example on the basis of a ring oscillator.
FIG. 2 is a block diagram of a simple ring oscillator 200 of the prior art, comprising N delay stages 202.1 to 202.N connected in series, and an inverted feedback path from the last stage to the first stage. In operation, N different clock phases may be obtained from the outputs of each of the stages 202.1 to 202.N. It is usual to ensure that each of the N delay stages 202.1 to 202.N are identical thus yielding an evenly spaced distribution of phases. The frequency at which the simple ring oscillator 200 will oscillate is determined by the sum of the intrinsic delays of each delay stage. Ways to achieve a frequency change, thus turning the simple ring oscillator 200 into a VCO include changing the supply voltage or changing an internal bias voltage of each delay stage. It is appreciated that such a simple VCO may have many shortcomings, including a strong dependency on process variations, highly variable output voltage, and a tuning range that may be quite narrow.
The simple ring oscillator 200 may be analyzed as a loop of N amplifier stages. The input-output transfer function at DC of the chain of amplifiers is the same one that a single inverter has, a 180° phase shift. This means that the closed loop has a negative feedback. This stabilizes the DC operating point of each stage right in the center (in the case where all stages are identical) of their linear range of input-output characteristic. Assuming that all stages in the ring are identical makes analysis easier, and there are also other reasons why the stages should be identical and equally loaded, including the facility to derive evenly spaced clock phases from the circuit. It thus gives us a large voltage swing and equal phase shift from stage to stage, which is a must requirement in some applications.
The magnitude of the overall small signal gain of the chain of N amplifiers starts dropping with the slope of N×20 dB/decade after the frequency of the dominant pole (the 3 dB point) of the individual amplifier. As well, the phase shift increases significantly in the vicinity of the 3 dB point.
FIG. 3 illustrates exemplary simulation plots of the small signal gain and phase of a chain of four (N=4) amplifier stages, as a function of frequency, based on an open loop arrangement of the simple ring oscillator 200 of FIG. 2. The GAIN plot (upper part of FIG. 3) and the PHASE plot (lower part of FIG. 3) share the same frequency scale, logarithmic frequency ordinates covering the range of 1 MHz to 10 GHz. The vertical (abscissa) scales are from −40 to +30 dB (GAIN plot) and 0 to −500 degrees (PHASE plot). The low frequency gain of the chain of amplifier stages is about 26 dB, and the phase is 0 degrees.
At the frequency (about 1 GHz) where the total extra phase rotation reaches 180 degrees the negative feedback in the closed loop of the simple ring oscillator 200 (FIG. 2) becomes positive. At this frequency the magnitude of overall gain is about 15 dB, i.e. greater than one, and the loop will oscillate.
Triggered by the intrinsic noise, the voltage swing during the very first period (after power on) is like noise: small, on order of pVs. But after each time the wave passes the loop it is getting multiplied by the open loop gain. Such an avalanche continues until the voltage swing becomes larger than the linear range of the input/output characteristic and, as a result of nonlinearities, the gain will drop and becomes exactly equal to one, and stable oscillation continues. The mechanism described here, of gain settling to one is based on finite supply voltage and the limited linear range of input/output characteristics of the transistors. Disadvantages of this type of simple ring oscillator are nonlinear distortion of the generated signal and slowing down of the oscillating frequency, but a big advantage is its simplicity.
The nonlinear distortions pollute a spectrum of the oscillator's output signal by adding higher harmonics. The main reason why the oscillating frequency is reduced is that the gate capacitance of the amplifier transistors increases when the transistors go into triode mode.
Another effect that is caused by nonlinearities is a low frequency flicker noise up conversion. The noise contributors are the bias circuits of the amplifiers and the amplifier transistors themselves. Ideally, if the VCO circuit could work in the linear range, we should not see skirts surrounding oscillating frequency in a spectrum plot of the output signal.
It appears that the amount of up converted noise could be minimized by controlling the voltage swing of the signal that is circulating in the ring to such a level that it will stay within the linear range of the ring amplifiers. This will increase the maximum oscillating frequency as well. The phase noise may be improved by controlling the voltage swing, but no circuit optimization was attempted to investigate by how much the phase noise could be improved by controlling the voltage swing. A circuit of automatic gain control would be required to keep the voltage swing at a small enough level. This would make the circuit more complicated. And it is not clear what will diminish faster—the noise power or the carrier power when the voltage swing is reduced.
From FIG. 3 it follows that the oscillating frequency of the simple ring oscillator is proportional to the bandwidth of the chain of amplifier stages.
The bandwidth (often the delay term is used instead of bandwidth) is process dependent; it varies with the temperature and the supply voltage; it drifts when bias voltage/current settles after power up; and it drifts with aging.
As a result the oscillating frequency is changing or drifting continuously. In addition to that the oscillator's intrinsic noise impacts the oscillating frequency as well.
In many applications the VCO oscillating frequency must be changed to different values, for example to track a reference clock in a PLL.
In order to control the VCO oscillating frequency, to compensate for frequency drift and to suppress the phase noise, the VCO may have two kinds of tuning: a) coarse control and b) continuous tuning.
Coarse tuning may be used to switch between specified oscillating frequencies. It could be used to compensate for frequency shift due to permanent factors such as a process, for example. An automatic tracking loop may also be needed. It could be activated just once after power up and reset in order to choose the desired frequency range.
Coarse tuning is usually implemented by switching components of the ring amplifiers, components whose parameters have direct impact on the amplifier's bandwidth—for example differential stage tail current, load, etc.
It is more challenging to implement continual tuning, especially when the tuning range should be wide enough to compensate for the impact of all factors that may affect the oscillating frequency, including process variation.
Continual tuning of a simple ring oscillator (FIG. 2) may be implemented by adjusting the bandwidth of the ring amplifiers, but because of the tuning range limitation, other architectures have become more popular. These are generally based on a form of multiple-pass loop architecture, see examples in the following references:    Yalcin Alper Eken, Student Member, IEEE, and John P. Uyemura, Senior Member, IEEE, “A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-um CMOS,” in IEEE journal of solid-state circuits, vol. 39, no. 1, January 2004, pp. 230-233;    “Multiple interconnected ring oscillator circuit,” U.S. Pat. No. 5,475,344 issued Dec. 12, 1995;    Edoardo Prete, Dirk Scheideler, Anthony Sanders, “A 100 mW 9.6 Gb/s Transceiver in 90 nm CMOS for next-generation memory interfaces,” Infineon, Munich, Germany, ISSCC 2006/SESSION 4/GIGABIT TRANSCEIVERS/4.5;    D.-Y. Jeong, S.-H. Chai, W.-C. Song, and G.-H. Cho, “CMOS current-controlled oscillators using multiple-feedback loop architectures,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1997, pp. 386-387;    L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage controlled ring oscillator based on three-stage subfeedback loops,” in Proc. Int. Symp. Circuits and Systems, Conf. Dig. Tech. Papers, 1997, pp. 386-387.
These published concepts are fundamentally based on a multiple-pass loop architecture similar to the feed-forward architecture shown in FIG. 4.
FIG. 4 is a block diagram of a typical feed-forward ring oscillator 400 of the prior art, comprising N (N=4) amplifier stages 402.1 to 402.4. The amplifier stages may be implemented with differential inputs and outputs, but for reasons of simplicity, single-ended circuits and signals are described. Each of the amplifier stages 402.1 to 402.4 includes three inputs, a primary input “P”, a secondary input “S” and a tuning input “T”. Each of the amplifier stages 402.1 to 402.4 further includes a non-inverting output 404, i.e. non-inverting outputs 404.1 to 404.4. The last amplifier stage 402.4 further includes an inverting output 406.4. When the amplifier stages 402.1 to 402.4 are implemented as differential circuits, at least the primary and secondary inputs “P” and “S” are differential, and each amplifier includes a differential output having both non-inverting and inverting terminals (404.i and 406.i, i=1 to 4). The tuning input “T” may be a single ended input, even when the remaining circuitry is differential. The tuning inputs “T” of all amplifier stages 402.1 to 402.4 may be connected to a common tuning voltage 408. The tuning voltage 408 may, for example, be generated by a loop filter (see the PLL 100 in FIG. 1, including the loop filter 108 and the VCO 112 which could be an instance of the feed-forward ring oscillator 400).
The primary connections of the feed-forward ring oscillator 400 are similar to connections of the simple ring oscillator 200 of FIG. 2, that is, the non-inverting output of each of the first N−1 amplifier stages 402.i is connected to the primary input of the next amplifier stage 402.i+1 and the inverting output 406.N of the Nth amplifier stage 404.N is connected to the primary input “P” of the first amplifier stage 402.1.
Thus, in the present example where N=4, the following are the primary connections:                the output 404.1 is connected to the input “P” of the amplifier stage 402.2;        the output 404.2 is connected to the input “P” of the amplifier stage 402.3;        the output 404.3 is connected to the input “P” of the amplifier stage 402.4;and the inverting output 406.4 is connected to the input “P” of the amplifier stage 402.1.        
In a set of secondary connections the input “P” of each amplifier stage 402.i is connected to the secondary input “S” of the next amplifier stage in the ring.
Thus, in the present example where N=4, the following are the secondary connections:                the output 404.1 is connected to the input “S” of the amplifier stage 402.3;        the output 404.2 is connected to the input “S” of the amplifier stage 402.4;        the output 404.3 is connected to the input “S” of the amplifier stage 402.1;and the inverting output 406.4 is connected to the input “S” of the amplifier stage 402.2.        
The secondary connections add auxiliary feed forward loops that work in conjunction with the primary loop of the basic (simple) ring oscillator topology. Within each amplifier stage adjustable portions of the signals arriving at the primary and secondary inputs “P” and “S” are amplified. The adjustment of the portions is controlled by the magnitude of the tuning voltage 408 that is fed to the “T” input of each amplifier stage. The purpose is to reduce the phase shift (i.e. the delay) of each amplifier in the ring, which results in an increase of the oscillating frequency as a higher proportion of the secondary signal is propagated.
Frequency tuning of the feed-forward ring oscillator 400 is thus achieved by adjusting the mix of the secondary inputs with the primary inputs in each amplifier stage 402. When the strength of the secondary inputs is set to zero, the feed-forward ring oscillator 400 behaves in a manner that is equivalent to the simple ring oscillator 200. By increasing the strength of the secondary inputs, the oscillating frequency is increased which has two disadvantages, the tuning range is limited by the high frequency characteristics of the circuitry, and the signal swing of the outputs decreases with the increasing tuning frequency.
In a VCO built on the principle of the feed-forward ring oscillator 400, the tuning range is limited and the VCO output signal swing decreasing when the tuned frequency is increased. This is illustrated in the following simulation plots.
FIG. 5 shows a simulation plot of three output signal waveforms (Flow, Fmedium, and Fhigh) at an output (any of 404.1 to 404.4) of the feed-forward ring oscillator 400 (FIG. 4), when the tuning voltage 408 is set to one of three different values to achieve a high, medium and low oscillating frequency. The scale of the ordinate is time in nanoseconds (nS) ranging from 15.0 to 17.0 nS suited to displaying a number of cycles at the frequencies of interest. The scale of the abscissa is voltage in Volts (V), ranging from 0.5 to 1.0 V. The plot in FIG. 5 shows waveforms at the positive output of a differential stage, thus of a single ended signal; the value of each corresponding differential output voltage swing is twice that of the single ended signal. The three output signal waveforms are sinusoids, oscillating with different frequencies and voltage swings:
The frequency of the output signal waveform Flow is approximately 5.8 GHz and its differential voltage swing between low and high peaks is approximately 0.807 V. The frequency of the output signal waveform Fmedium is approximately 7.24 GHz and its differential voltage swing is approximately 0.536 V. The frequency of the output signal waveform Fhigh is approximately 9.2 GHz and its differential voltage swing is approximately 0.247 V.
FIG. 6 shows simulation plots of the differential voltage swing and the oscillating frequency of the feed-forward ring oscillator 400 (FIG. 4) when the tuning voltage is varied between about −0.2 and +0.2 Volt. The upper graph (“Differential Voltage Swing”) has a vertical voltage scale ranging from 0.2 V to 0.8 V while the lower graph (“Frequency”) has a vertical frequency scale ranging from 5.0 GHz to 10.0 GHz.
As the “Differential Voltage Swing” graph shows, the differential voltage swing varies from about 0.8 V to about 0.25 V as the tuning voltage is increased over the tuning range from −0.2 V to about 0.15 V. Over the same tuning range, the “Frequency” graph shows the oscillating frequency to increase from about 5.9 GHz to about 9.2 GHz. When the tuning voltage is increased beyond about the upper limit of the tuning range at about 0.15 V, the oscillation stops because at that point the open loop gain of the exemplary feed-forward ring oscillator becomes less than zero.
The foregoing analysis shows that the tuning range covers less than an octave in frequency, and the corresponding voltage swing varies by a large amount. These properties of the feed-forward ring oscillator 400 make this type of oscillator unsuitable as a VCO in a system which requires a much wider tuning range. The drop in voltage swing also makes the oscillating signal difficult to use directly, without additional amplification stages which will add to the cost and contribute additional jitter.